Modules

Modules are fundamental building blocks of a logical circuit design. They encapsulate the structural and behavioural description of a digital circuit. The external interface, internal state, assignments and hierarchy are defined by a module instance.

Module Definition

module axpb(
  input logic[32] a,
  input logic[32] x,
  input logic[32] b,
  output logic[32] result
)
endmodule;

class MyParamStruct(n: Int) extends Bundle {
  val a = Bool()
  val b = Vec(n, Bool())
}

module(
  input logic[31:0] a,
  input logic[31:0] x,
  input logic[31:0] b,
  output logic[31:0] result
)
endmodule;

Defining Module Logic

Combinatorial vs Registered Logic

By default, operations in Nail are combinatorial.

module axpb(
  input logic[32] a,
  input logic[32] x,
  input logic[32] b,
  output logic[32] result  
)
  // This operation is combinatorial (as if inside of always_comb in
  // SystemVerilog).
  let ax = a * x;
  // This operation is also combinatorial
  assign result = ax + b;
endmodule

Registered Logic

Nail makes the following assumptions about registered logic:

1. There is only one clock/reset domain in the design.
2. There is a single defined update to the register.

Here is Nail’s simple syntax for registered logic:

// Define a register of signal_t, initialized to initializer on reset.
reg<signal_t> example_register(initializer);
// Update the value of this register. Subsequent updates will raise
// an error.
example_register <= updated_value;