Interfaces operate on a level above data types. They augment data with
information about the directionality of signals.
The input and output keywords in Nail behave the same as in
SystemVerilog.
Nail
input logic a;
output logic[4] b;
Chisel
val a = Input(Bool())
val b = Output(UInt(4.W))
SystemVerilog
input logic a;
output logic[3:0] b;
The interface keyword in Nail will generate a SystemVerilog interface.
The generated interface will contain three modports: forward, flipped
and monitor.
Nail
interface my_interface {
input logic a;
output logic[32] b;
}
Chisel
class MyInterface extends Bundle {
val a = Input(Bool())
val b = Output(UInt(32.W))
}
SystemVerilog
interface my_interface;
logic a;
logic [31:0] b;
modport forward (input a, output b);
modport flipped (output a, input b);
modport monitor (input a, input b);
endinterface
Nail supports nesting interfaces within other interfaces.
Nail
interface inner_if {
input logic valid;
input logic write;
input logic[32] addr;
input logic[32] data;
output logic ready;
};
interface outer_if {
inner_if req;
output logic[32] result;
};
Chisel
val a = Input(Bool())
val b = Output(UInt(4.W))
SystemVerilog
interface inner_if;
input logic valid;
input logic write;
input logic[32] addr;
input logic[32] data;
output logic ready;
endinterface
interface outer_if;
inner_if req;
output logic[32] result;
endinterface;
TODO(derekjchow): Check if this is necessary?